1. Field of the Invention
The present invention relates to a solid-state imaging device and a camera. More specifically, the present invention relates to a solid-state imaging device capable of correcting shading of a picked-up (or captured) image and a camera using the solid-state imaging device of the above mentioned type.
2. Description of the Related Art
Nowadays, solid-state imaging devices such as CMOS type image sensors are being widely used as image input devices of imaging apparatuses mounted on various mobile terminal appliances such as mobile phones and of imaging apparatuses such as digital still cameras and digital video cameras (for example, see Japanese Patent Laid-Open Publication No. 10-126697).
FIG. 6 is a schematic diagram illustrating a CMOS type image sensor. The CMOS type image sensor includes a pixel array unit 202 in which many pixels 201 having photoelectric converting elements are arrayed in a matrix and a vertical scanning circuit 203 configured to select the pixels in the pixel array unit on a row by row (line by line) basis to control a shutter-releasing operation and a reading-out operation of each pixel. The image sensor also includes a column signal processing unit 204 configured to read out signals from the pixel array unit on a row by row basis and to perform predetermined signal processing operations (for example, a CDS process, an AGC process and an analog-to-digital converting process) on the signals on a column by column basis. The image sensor further includes a horizontal scanning circuit 206 configured to select the signals from the column signal processing unit on a signal by signal basis to guide the selected signal to a horizontal signal line 205 and a signal processing unit 207 configured to convert the signal sent from the horizontal signal line into data of an intended output form. The image sensor further includes a timing generator 208 configured to supply various pulse signals necessary for execution of operations of respective units on the basis of a reference clock. Incidentally, the CDS process is a process of removing fixed pattern noise induced by the variation in threshold values of transistors constituting each pixel and ADC process is an automatic gain controlling process.
As shown in FIG. 7, each of the pixels 201 arranged in the pixel array unit has a circuit configuration including a transfer transistor 102, a reset transistor 103, an amplification transistor 104 and a selection transistor 105, in addition to a photoelectric converting element (for example, a photodiode) 101. FIG. 7 shows an example of a circuit using N-channel type MOS transistors as the transistors 102 to 105.
The transfer transistor 102 is connected between a cathode electrode of the photodiode 101 and an FD (floating diffusion) unit 106 and a gate electrode of the transfer transistor 102 is connected to a transfer control line 111 to which a transfer gate pulse TG is applied. A drain electrode of the reset transistor 103 is connected to a power source Vdd, its source electrode is connected to the FD unit 106 and its gate electrode is connected to a reset control line 112 to which a reset pulse RS is applied.
A gate electrode of the amplification transistor 104 is connected to the FD unit 106, its drain electrode is connected to the power source Vdd and its source electrode is connected to a drain electrode of the selection transistor 105. A gate electrode of the selection transistor 105 is connected to a selection control line 113 to which a selection pulse SEL is applied and its source electrode is connected to a vertical signal line 216. The vertical signal line 216 is connected to a constant-current source 217 configured to supply a constant current to the vertical signal line 216 and is also connected to the column signal processing unit 204.
FIG. 8 is a schematic diagram illustrating a sectional structure of pixel constitutional parts other than the amplification transistor 104 and the selection transistor 105.
N-type diffusion regions 132, 133 and 134 are formed on a surface layer of a P-type substrate 131. A gate electrode 135 is formed above a part of the P-type substrate 131 between the N-type diffusion regions 132 and 133 and a gate electrode 136 is also formed above a part of the P-type substrate 131 between the N-type diffusion regions 133 and 134 respectively via gate oxide (SiO2) films not shown.
In a corresponding relation between the examples shown in FIGS. 7 and 8, the photodiode 101 is formed by P-N junction between the P-type substrate 131 and the N-type diffusion region 132. The transfer transistor 102 is constituted by the N-type diffusion region 132, the N-type diffusion region 133 and the gate electrode 135 formed above the part between the regions 132 and 133. The reset transistor 103 is constituted by the N-type diffusion region 133, the N-type diffusion region 134 and the gate electrode 136 formed above the part between the regions 133 and 134.
The N-type diffusion region 133 constitutes the FD unit 106 and is electrically connected to the gate electrode of the amplification transistor 104. A supply potential is applied from the power source Vdd to the N-type diffusion region 134 acting as a drain electrode of the reset transistor 103. A light-shielding layer 137 is laid over the upper surface of the P-type substrate 131 except a part on which the photodiode 101 is formed.
Next, a circuit operation of the pixel 201 will be described with reference to a wave-form chart in FIG. 9. In FIG. 9, φRSn is a reset pulse on an n-th line, φTGn is a transfer gate pulse on the n-th line and φSELn is a selection pulse on the n-th line. Also, in FIG. 9, A is a resetting operation duration, B is an accumulating operation duration, C is a transferring operation duration and D is a reading-out operation duration.
In the pixel on the n-th line, first, the reset pulse RSn to be applied to the reset transistor 103 and the transfer gate pulse TGn to be applied to the transfer transistor 102 are set at high levels (H levels) for a time period between times t31 and t32. As a result, useless charges accumulated in the photodiode 101 and the FD unit of the pixel on the n-th line are removed (a resetting operation).
Next, at the time t32, the reset pulse RSn to be applied to the reset transistor 103 and the transfer gate pulse TGn to be applied to the transfer transistor 102 are set at low levels (L levels). As a result, accumulation of signal charges which have been photoelectric-converted using the photodiode 101 of the pixel on the n-th line is started (an
Then, at a time t34, the transfer gate pulse TGn to be applied to the transfer transistor 102 is set at the H level to start an operation of transferring the signal charges from the photodiode 101 to the FD unit 106. Then, at a time t35, the transfer gate pulse TGn is set at the L level to terminate the operation of transferring the signal charges from the photodiode 101 to the FD unit 106 (a transferring operation). Incidentally, a time period from the time t32 to the time t35 is set as a time period for which the signal charges are accumulated in a pixel (hereinafter, referred to as a signal charge accumulation time period of the pixel) on the n-th line.
When the selection pulse SELn to be applied to the selection transistor 105 is set at the H level at the completion of the signal charge transferring operation in the pixel on the n-th line, the signal charge held in the FD unit 105 is converted into a voltage signal to be output (a reading-out operation).
In the pixel on the (n+1)-th line, the resetting operation, the accumulating operation, the transferring operation and the reading-out operation are performed at timings different from those of the operations of the pixel on the n-th line.
Specifically, a reset pulse RS(n+1) to be applied to the reset transistor 103 and a transfer gate pulse TG(n+1) to be applied to the transfer transistor 102 are set at the H levels for a time period between the times t32 and t33. As a result, useless charges accumulated in the photodiode 101 and the FD unit 106 of the pixel on the (n+1)-th line are removed.
Next, at the time t33, the reset pulse RS(n+1) to be applied to the reset transistor 103 and the transfer gate pulse TG(n+1) to be applied to the transfer transistor 102 are set at the L levels. As a result, accumulation of signal charges which have been photoelectric-converted using the photodiode 101 of the pixel on the (n+1)-th line is started.
Then, at a time t35, the transfer gate pulse TG(n+1) to be applied to the transfer transistor 102 is set at the H level to start the operation of transferring the signal charges from the photodiode 101 to the FD unit 106. At a time t36, the transfer gate pulse TG(n+1) is set at the L level to terminate the operation of transferring the signal charges from the photodiode 101 to the FD unit 106. Incidentally, a time period from the time t33 to the time t36 is set as a signal charge accumulation time period of the pixel on the (n+1)-th line.
When a selection pulse SEL(n+1) to be applied to the selection transistor 105 is set at the H level at the completion of the operation of transferring the signal charges in the pixel on the (n+1)-th line, the signal charge held in the FD unit 106 is converted into a voltage signal to be output.
In an existing CMOS type image sensor, signal charge accumulation time periods are the same as one another among pixels regardless of to which row the pixel concerned belongs. For example, the time period between the times t32 and t35 which is the signal charge accumulation time period of the pixel on the n-th line is the same as the time period between the times t33 and t36 which is the signal charge accumulation time period of the pixel on the (n+1)-th line.
Incidentally, in a camera system using a solid-state imaging device such as a CMOS type image sensor, in a peripheral area of the pixel array unit (a light receiving region) of the solid-state imaging device, incident light sent from an optical system is not vertically incident on the solid-state imaging device and is incident on the device at a predetermined angle. As a result, shading that the sensitivity attained in the peripheral area of the pixel array unit (the light receiving region) of the solid-state imaging device is lower than that attained in a central area of the pixel array unit (the light receiving region) of the solid-state imaging device may occur.
In order to prevent the shading as mentioned above, there has been proposed a method in which an output signal obtained from each pixel is converted into digital data and is then subjected to arithmetic operations to correct the shading (for example, see Japanese Laid-Open Patent Publication No. 09-69980).